FIG. 11 is a plan view showing a layout of a known semiconductor device in which a large number of MIS transistors (hereinafter, referred to as MISFETs) are arranged. As shown in FIG. 11, various types of active regions in which mutually different numbers of MISFETs are arranged at mutually different densities are provided in the semiconductor device, being surrounded by a trench isolation Ris. Hereinafter, an active region in which gates 101 of three or more respective MISFETs are continuously arranged without being separated by the trench isolation Ris will be referred to as a continuous active region R101, an active region in which only a gate 104 of a MISFET is placed will be referred to as a discontinuous active region R102, and an active region in which gates 106 of two respective MISFETs are disposed will be referred to as two-input active region R103. Dummy gates 107 are arranged on the trench isolation Ris of the semiconductor device so as to increase the accuracy in patterning for gates using a line-and-space pattern.
In addition, as shown in FIG. 11, a distance L101 between one of the gates 101 of the MISFETs located at each end thereof in the continuous active region R101 and the trench isolation Ris, a distance L102 between the gate electrode 104 of the MISFET in the discontinuous active region R102 and the trench isolation Ris, and a distance L103 between each of the gates 106 of the MISFETs in the two-input active region R103 and the trench isolation Ris, differ from one another.
In this manner, the known semiconductor device is configured to have a layout in which transistors in continuous active regions, transistors in discontinuous active regions and transistors in two-input active regions are mixed, in order to minimize the area occupied by the device.
It is considered that the reason why the known semiconductor device has been designed in the manner as described above is based on the premise that the performance of a semiconductor device is determined by the gate length and gate width of MISFETs. However, experiments done by the present inventors have revealed that the performance of a semiconductor device provided with recent MISFETs that have been minimized is changeable depending not only on the gate length and gate width of the MISFETs but also on the layout of the active regions. More specifically, even for MISFETs having the same circuit configuration, operating speeds of the respective MISFETs vary depending on the layouts thereof. That is to say, the performance of the whole semiconductor device is also affected by the layouts.